Cadence Unveils AI Models With Nvidia, Lifting Chip Design Quality by Up to 30%

Key Facts

Cadence announced its Maestro AI model portfolio on October 26, saying it will support its AI agents in semiconductor and systems design workflows. The company said initial results in design workflows showed output quality improvements of up to 30% and token efficiency up to 5 times higher than general foundation models. The figures put the specialized model portfolio at the center of Cadence’s pitch to expand the use of its agents across engineering design tools. The company said the comparison concerns output quality and token efficiency, not a general improvement in economic efficiency. The first models are expected to be made available to selected customers through an early access program in the fourth quarter of 2026.

The portfolio combines, according to Cadence, domain-specific large language models that have undergone post-training, trained decision models and self-improving agent skills. Maestro includes Nvidia’s Nemotron models alongside other models, and can later be adapted using customers’ data, designs and workflows. Cadence says this customization allows the models to be aligned with each customer’s design contexts and engineering processes. The portfolio also integrates with the company’s electronic and systems design and automation tools, as well as reinforcement learning loops. The company presents these components as an interconnected AI agent system, rather than a single language model.

Cadence attributes the announced improvement to an integrated learning environment that brings together its domain expertise, curated engineering data sets, agents, and design and evaluation tools. The environment includes electronic design and automation tools, as well as evaluation tools that compare outputs with engineering objectives and constraints. According to the company, it uses deterministic analyzers to check results against those objectives and constraints. This approach places the models within an engineering workflow that includes generating and evaluating outputs, rather than relying on a text response alone. In an explanation published by Cadence on October 22, it said the engineer defines objectives, reviews evidence, verifies results and evaluates proposed changes, and remains responsible for design decisions and their approval.

The option to control deployment is one element of Cadence’s offer for customers that want to keep their design environments under their control. The full environment, including agents, the Maestro portfolio and design tools, can run on Cadence’s secure cloud, secure public clouds or infrastructure controlled by the customer. The two companies are also working to integrate Nvidia’s OpenShell to strengthen agent security. Post-training on each customer’s data, designs and workflows combines customization with flexibility in choosing a deployment environment. Cadence did not provide a separate timeline for the availability of each deployment option, while it set the fourth quarter of 2026 for the first models to reach early access customers.

Maestro enters a market where chip design tool companies are competing to bring AI into engineering workflows. Reuters reported that Synopsys announced on September 30 that it was developing an AI model with OpenAI, running on infrastructure hosted by the latter. In Reuters’ description, Cadence’s approach differs by allowing the environment to run on-site at the customer, while the Synopsys announcement tied the model to OpenAI’s hosted infrastructure. Paul Cunningham, Cadence’s senior vice president, said the company “is pursuing both open and closed-weight approaches equally,” and that working with commercial labs “is part of the Maestro vision.” This reflects Cadence’s effort to keep its portfolio open to multiple approaches and models, according to its statements.

Cadence cites other examples of its agents’ performance in specific design tasks, separate from the initial figures for the Maestro portfolio. In early evaluations published by the company on October 22, its ChipStack agent recorded average reductions of 24% in area and 18% in power compared with code generation using foundation models alone, with 100% functional accuracy across the RTL designs included in the evaluation. The company also said its VeraStack agent achieved a 95% productivity improvement in generating SKILL code using natural language prompts and Virtuoso design context. It added that design closure was 60% faster in a test flow for analog and radio-frequency design migration at 6 GHz. In a separate example, the chief operating officer of Socionext said the company is deploying Cadence’s InnoStack agent in production and expects overall productivity gains of up to 5 times while maintaining design quality.